Method for forming super-steep retrograded channel (SSRC) for cmos transistor using rapid laser annealing to reduce thermal budget

ABSTRACT

A method for making a ULSI MOSFET chip includes forming a sacrificial gate on a substrate along with activated source and drain regions, but without initially establishing a doped channel region. The polysilicon portion of the sacrificial gate is then removed and a neutral ion species such as Silicon or Germanium is implanted between the source and drain regions in the region that is to become the doped channel region. A dopant substance is next implanted into the channel region, which is then exposed to ultra-rapid thermal annealing to cause the dopant to form a box-like, super-steep retrograded channel profile. The gate is then re-formed over the now activated doped channel region.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductorfabrication, and more particularly to methods for fabricating improvedultra-large scale integration (ULSI) semiconductor devices such as ULSImetal oxide silicon field effect transistors (MOSFETs).

BACKGROUND OF THE INVENTION

[0002] Semiconductor chips or wafers are used in many applications,including as processor chips for computers, and as integrated circuitsand as flash memory for hand held computing devices, wirelesstelephones, and digital cameras. Regardless of the application, it isdesirable that a semiconductor chip hold as many circuits or memorycells as possible per unit area. In this way, the size, weight, andenergy consumption of devices that use semiconductor chipsadvantageously is minimized, while nevertheless improving the memorycapacity and computing power of the devices.

[0003] A common circuit component of semiconductor chips is thetransistor. In ULSI semiconductor chips, a transistor is established byforming a poly silicon gate on a silicon substrate, and then forming asource region and a drain region in the substrate beneath the gate byimplanting appropriate dopant materials into the areas of the substratethat are to become the source and drain regions. The gate is insulatedfrom the substrate by a thin gate oxide layer, with small portions ofthe source and drain regions, referred to as “extensions”, extendingtoward and virtually under the gate.

[0004] Between the source and drain regions and under the gate oxidelayer is a channel region, a portion of which is doped. The dopedportion of the channel region typically is doped early in thefabrication process, with the channel dopant usually being implantedduring the steps of forming the gate and source and drain regions. Thisgenerally-described structure cooperates to function as a transistor.

[0005] To suppress deleterious “short channel” effects such as thresholdvoltage roll-off (i.e., transistor operation at below intendedvoltages), it is important that the dopant profile of the channel besteep. Stated differently, it is important that virtually all of thedopant in the channel region be concentrated within a relatively smallarea that is to function as the doped portion of the channel, withlittle or no dopant being located outside this relatively small dopedregion between the small doped region and the source and drain regions.With this in mind, it is desirable that the dopant profile of thechannel region be a so-called “super-steep retrograded channel” (SSRC)profile.

[0006] As recognized by the present invention, semiconductor fabricationentails considerable heating during processing. Accordingly, structuressuch as doped channel regions that are established relatively early inthe process are exposed to more heat than are structures formedrelatively late in the process. As further recognized herein, however,exposing a channel region that has been doped relatively early in themanufacturing process to subsequent heating steps can cause the dopantin the channel to thermally diffuse and, hence, can cause the dopantprofile of the channel undesirably to spread. Fortunately, the presentinvention addresses this problem.

BRIEF SUMMARY OF THE INVENTION

[0007] A method for establishing a transistor on a semiconductor deviceincludes providing a semiconductor substrate, and forming a sourceregion and a drain region in the substrate. Also, a sacrificial gate isformed above the source and drain regions, without forming a dopedchannel region between the source and drain regions. Then, thesacrificial gate is removed and a neutral ion species is implanted inthe substrate between the source and drain regions to define anamorphous region. A dopant is implanted in the amorphous region, and theamorphous region is then heated to activate the dopant and therebyestablish a doped channel region. Following channel activation, a gatestack is established above the doped channel region.

[0008] In a preferred embodiment, the heating step is accomplished byheating the amorphous region to no more than nine hundred fifty degreesCelsius (950° C.), and more preferably to no more than nine hundreddegrees Celsius (900° C.), by laser annealing. Specifically, theamorphous region is irradiated with a laser for no more than tennanoseconds, and more preferably for no more than five nanoseconds, suchthat the temperature of the amorphous region does not exceed ninehundred fifty degrees Celsius (950° C.). A semiconductor device madeaccording to the present method, and a digital processing apparatusincorporating the device, are also disclosed.

[0009] In another aspect, a method is disclosed for making anultra-large scale integration (ULSI) semiconductor device. The methodincludes forming source and drain regions in a semiconductor substrateusing a first activation temperature, and then forming a doped channelregion between the source and drain regions using a second activationtemperature less than the first activation temperature.

[0010] In still another aspect, a semiconductor device includes asemiconductor substrate, a transistor gate on the substrate, and sourceand drain regions in the substrate below the gate. A channel region isbetween the source region and the drain region. Also, an activateddopant implant is in the channel region, as is a neutral ion speciesimplant.

[0011] Other features of the present invention are disclosed or apparentin the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.

BRIEF DESCRIPTION OF DRAWINGS

[0012]FIG. 1 is a schematic diagram of a semiconductor device madeaccording to the present invention, shown in combination with a digitalprocessing apparatus;

[0013]FIG. 2 is a flow chart showing the steps of the present invention;

[0014]FIG. 3 is a side view of the device after forming the source anddrain and sacrificial gate;

[0015]FIG. 4 is a side view of the device after TEOS layer deposition;

[0016]FIG. 5 is a side view of the device after the sacrificial gate hasbeen removed;

[0017]FIG. 6 is a side view of the device after implanting a neutral ionspecies in the substrate to establish the amorphous region;

[0018]FIG. 7 is a side view of the device after implanting dopant intothe amorphous region to establish a doped channel region;

[0019]FIG. 8 is a side view of the device after annealing the dopedchannel region to establish a super-steep retrograded channel dopingprofile; and

[0020]FIG. 9 is a side view of the device after forming the gate.

DETAILED DESCRIPTION OF THE INVENTION

[0021] Referring initially to FIG. 1, a semiconductor device embodied asa chip 10 is shown incorporated into a digital processing apparatus suchas a computer 12. The chip 10 is made in accordance with the belowdisclosure.

[0022] Now referring to FIGS. 2 and 3, as indicated at block 14 in FIG.2 and as shown in FIG. 3, a silicon substrate 16 is provided. Asacrificial gate 18 also is formed on the silicon substrate 16 usingconventional semiconductor fabrication techniques including low pressurechemical vapor deposition (LPCVD) and appropriate etching andlithography. As shown, the sacrificial gate 18 includes a thininsulating gate oxide layer 20 that faces the substrate 16 and a gatepolysilicon stack 22 on the gate oxide layer 20. Additionally, nitridesidewall spacers 24 are deposited on the substrate 16 and etched inaccordance with well-known principles to establish the illustratedshoulder configuration around the sides 26 of the gate 18 as shown.Activated source and drain regions 28, 30 are also formed in thesubstrate 16. The structure shown in FIG. 3 and described thus far isconventionally formed using temperatures of about one thousand degreesCelsius (1000° C.), with the exception that no doped channel region hasbeen formed in the substrate 16 beneath the gate 18.

[0023] Proceeding to block 32 in FIG. 2 and referring to FIG. 4, anoxide layer 34 is formed on the substrate 16 on both sides of thesacrificial gate 18. Preferably, the oxide layer 34 is tetraethoxysilane (TEOS). Then, as indicated at block 36 in FIG. 2 and as shown inFIG. 5, the polysilicon stack 22 of the sacrificial gate 18 is removedby, e.g., wet etching.

[0024] Referring now to block 38 in FIG. 2 and considering FIG. 6, anamorphous region 40 in the substrate 16 is implanted with a neutral ionspecies 42. In one preferred embodiment, the neutral ion species 42includes Silicon (Si) or Germanium (Ge). The implanting of the neutralion species 42 precisely establishes the rectangular contour shown ofthe amorphized region 40. As an alternative to Silicon or Germanium, theneutral ion species 42 can be an ion of, e.g., Boron Fluoride (BF₂),Arsenic (As), Boron (B), or Phosphorous (P).

[0025] Proceeding to block 44 in FIG. 2 and now considering FIG. 7, anappropriate dopant substance 46, represented by small “x”s in FIG. 7, isimplanted into the substrate 16. It is to be understood that as shown,the dopant profile (represented by the line 48) in the portion of thesubstrate that includes the amorphized region 40 rises from a level ofnear zero at a point 50 near the surface of the substrate 16 to a peak52 within the amorphized region 40, and then the dopant profile 48tapers off deeper into the substrate 16.

[0026] To render the desired box-like, super-steep retrograded channel(SSRC) dopant profile, the amorphous region 40 is annealed at block 54in FIG. 2 to render an activated doped channel region 56, shown in FIG.8, having the box-like SSRC profile 58 shown. More specifically, duringheating, dopant in the substrate 16 that is near the doped channelregion 56 is redistributed into the doped channel region 56, thusachieving a relatively constant dopant concentration in the dopedchannel region 56 as shown and a relatively constant, near-zero dopantconcentration outside the channel region 58 between the source and drainregions 28, 30. During heating, the gate oxide layer 20 is removed.

[0027] In the presently preferred embodiment, the doped channel region56 is heated to no more than nine hundred fifty degrees Celsius (950°C.), and more preferably to no more than nine hundred degrees Celsius(900° C.), by ultra-rapid laser annealing. To undertake this annealing,the channel portion 56 is irradiated by a laser for no more than tennanoseconds, and more preferably for no more than five nanoseconds.

[0028] From block 54, the process moves to block 60, wherein a gatestack 62 is formed on the substrate 16 above the doped channel region56. Processing, including the forming of contacts and interconnects, iscompleted at block 64.

[0029] While the particular METHOD FOR FORMING SUPER-STEEP RETROGRADEDCHANNEL (SSRC) FOR CMOS TRANSISTOR USING RAPID LASER ANNEALING TO REDUCETHERMAL BUDGET as herein shown and described in detail is fully capableof attaining the above-described objects of the invention, it is to beunderstood that it is the presently preferred embodiment of the presentinvention and is thus representative of the subject matter which isbroadly contemplated by the present invention, that the scope of thepresent invention fully encompasses other embodiments which may becomeobvious to those skilled in the art, and that the scope of the presentinvention is accordingly to be limited by nothing other than theappended claims, in which reference to an element in the singular is notintended to mean “one and only one” unless explicitly so stated, butrather “one or more”. Indeed, although a single transistor structure isshown in the drawings for clarity, the skilled artisan will appreciatethat the chip 10 can include plural transistors, each substantiallyidentical to that shown, as well as other circuit components. Allstructural and functional equivalents to the elements of theabove-described preferred embodiment that are known to those of ordinaryskill in the art are expressly incorporated herein by reference and areintended to be encompassed by the present claims. Moreover, it is notnecessary for a device or method to address each and every problemsought to be solved by the present invention, for it to be encompassedby the present claims. Furthermore, no element, component, or methodstep in the present disclosure is intended to be dedicated to the publicregardless of whether the element, component, or method step isexplicitly recited in the claims. No claim element herein is to beconstrued under the provisions of 35 U.S.C. §112, sixth paragraph,unless the element is expressly recited using the phrase “means for”.

What is claimed is:
 1. A method for establishing at least one transistoron a semiconductor device, comprising: providing a semiconductorsubstrate; forming a source region and a drain region in the substrateand a sacrificial gate above the source and drain regions, withoutforming a doped channel region between the source and drain regions;then removing the sacrificial gate; implanting at least one neutral ionspecies in the substrate between the source and drain regions to definean amorphous region; implanting at least one dopant in the amorphousregion; heating at least the amorphous region to activate the dopant andthereby establish a doped channel region; and forming a gate above thedoped channel region.
 2. The method of claim 1 , wherein the heatingstep is accomplished by heating the amorphous region to no more thannine hundred fifty degrees Celsius (950° C.).
 3. The method of claim 2 ,wherein the heating step is accomplished by heating the amorphous regionto no more than nine hundred degrees Celsius (900° C.).
 4. The method ofclaim 1 , wherein the heating step is accomplished by laser annealing.5. The method of claim 4 , wherein the heating step is accomplished byirradiating the amorphous region with a laser for no more than tennanoseconds.
 6. The method of claim 5 , wherein the heating step isaccomplished by irradiating the amorphous region with a laser for nomore than five nanoseconds.
 7. The method of claim 4 , wherein theheating step is accomplished by irradiating the amorphous region with alaser such that the temperature of the amorphous region does not exceednine hundred fifty degrees Celsius (950° C.).
 8. The method of claim 1 ,wherein the neutral ion species includes at least one of: Silicon (Si)and Germanium (Ge).
 9. A semiconductor device made according to claim
 1. 10. A digital processing apparatus incorporating the device of claim
 9. 11. A method for making an ultra-large scale integration (ULSI)semiconductor device, comprising: forming source and drain regions in asemiconductor substrate using a first activation temperature; thenforming a doped channel region between the source and drain regionsusing a second activation temperature less than the first activationtemperature.
 12. The method of claim 11 , wherein the second activationtemperature is induced by irradiating a portion of the substrate with alaser for less than ten nanoseconds such that the second temperaturedoes not exceed nine hundred fifty degrees Celsius (950° C.).
 13. Themethod of claim 12 , wherein the second activation temperature isinduced by irradiating a portion of the substrate with a laser for lessthan five nanoseconds such that the second temperature does not exceednine hundred degrees Celsius (900° C.).
 14. The method of claim 11 ,further comprising: implanting at least one neutral ion species in thesubstrate between the source and drain regions to define an amorphousregion; implanting at least one dopant in the amorphous region; heatingat least the amorphous region to the second activation temperature toactivate the dopant and thereby establish a doped channel region; andforming a gate above the doped channel region.
 15. The method of claim14 , wherein the neutral ion species includes at least one of: Silicon(Si) and Germanium (Ge).
 16. A semiconductor device made according toclaim 11 .
 17. A digital processing apparatus incorporating the deviceof claim 16 .
 18. A semiconductor device including: at least onesemiconductor substrate; at least one transistor gate on the substrate;source and drain regions in the substrate below the gate; a channelregion between the source region and the drain region; at least oneactivated dopant implant in the channel region; and at least one neutralion species implanted in the dopant region.
 19. A digital processingapparatus incorporating the device of claim 18 .